S9S12G48BCLC NXP
| Available |
S9S12G48BCLC NXP
S12 CPU is a high-speed 16-bit processing unit:
• Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
• Includes many single-byte instructions. This allows much more efficient use of ROM space.
• Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
On-chip flash memory on the MC9S12G-Family family features the following:
• Up to 240 Kbyte of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
• Up to 4 Kbyte EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads
S12 CPU is a high-speed 16-bit processing unit:
• Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
• Includes many single-byte instructions. This allows much more efficient use of ROM space.
• Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
On-chip flash memory on the MC9S12G-Family family features the following:
• Up to 240 Kbyte of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
• Up to 4 Kbyte EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads
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